Five-level topology units and inverter thereof

ABSTRACT

Disclosed are five-level topology units and inverter thereof without an extra boosting circuit wherein the cost is reduced by using only one AC filtering inductor and high efficiency is achieved for the absence of the extra boosting circuit and, furthermore, wherein the leakage current is eliminated substantially by using the half-bridge inverter module. The five-level inverter including the five-level topology unit without an extra circuit to raise input voltage (i.e. Boost circuit) is able to output the same AC power as the five-level full bridge inverter under the same working condition.

RELATED APPLICATION

This application claims the benefit of the filing date of U.S. Provisional Application No. 62/109,413, filed on Jan. 29, 2015, the content of which is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

The invention relates to five-level topology units and inverter circuits, especially for the renewable energy system.

BACKGROUND

With the increasing threat of global energy and serious environmental problem, the renewable energy has been developing fast. Photovoltaic industry has an extensive future as its resources are plentiful and widespread. It is an important issue to lower cost and improve efficiency for photovoltaic system.

Inverter is used to convert DC from photovoltaic arrays into AC in photovoltaic system. There are two kinds of grid-connected inverters. They are isolated and non-isolated ones. The transformer is used in the former to keep human electrically safe. But because of its power loss and huge volume, it results in many problems, such as low efficiency end power density, end high cost. Therefore, the non-isolated inverter in photovoltaic system is popular. However, there is a common mode loop circuit for the absence of transformer in the non-isolated inverter system. The high frequency and common mode current in the loop circuit leads to electromagnetic interference, and at the same time, it is dangerous to devices and human. So the high frequency and common mode current becomes a critical issue to be solved for the non-isolated inverter system.

There are two kinds of non-isolated inverters in photovoltaic system.

The first kind of inverter is symmetry in topology and it has double AC filtering inductors. Full bridge inverter circuit is usually of this kind. No extra circuit in the full bridge is needed to boost input voltage in many cases since it is enough for half of that of the halt-bridge. But it is difficult for the full bridge inverter to cancel substantially the high frequency leakage current because of the parasitic factors within the inverter system. The improvements of conventional H4 full bridge circuit ere made to reduce the high frequency leakage current so that it meets this industry standard. However, it costs much because the two AC filtering inductors' magnetic cores am not common for the symmetry mode.

The second kind of inverter is non-symmetry and it has single AC filtering inductor. Half bridge and mid-point damped inverter circuits are examples of this kind. The terminal of utility grid is connected with the mid-point of DC input voltage. The parasitic capacitor voltage is constant so that the leakage current is eliminated substantially. However, it needs an extra circuit to boost input voltage as it is twice of that of the first kind. The extra circuit lowers efficiency.

So it can be seen that if the second kind of inverter can work normally without the extra boosting circuit, it has obvious advantages over the first kind in low cost and high efficiency.

For the sake of brevity, the term “full bridge inverter” as used herein is intended to refer to the said first kind of inverter and the term “half bridge inverter” is intended to represent the said second kind.

In addition, five-level inverter is becoming populate improve efficiency.

SUMMARY

Provided herein are a five-level topology unit and inverter thereof to solve the above problems. They are non-isolated. To make sure the current flows in both directions, each semiconductor switch is connected in reverse parallel with a diode. For the sake of brevity, the term “bidirectional switch” as used herein is intended to refer to a semiconductor switch connected in reverse parallel with a diode.

The five-level topology unit is used with a first DC power supply and a second DC power supply. The negative terminal of the first DC power supply is connected in series with the positive terminal of the second DC power supply. The five-level topology unit comprises: a floating capacitor that is charged by the first DC power supply or the second DC power supply; and a half-bridge inverter module that outputs five mutually different voltage levels including zero; wherein either the first DC power supply or l the second DC power supply provides power for the half-bridge inverter module; or either the first DC power supply or the second DC power supply added algebraically to the floating capacitor provides power for the half-bridge inverter module.

Also provided herein is a five-level topology unit comprising: a first DC power supply and a second DC power supply whose positive terminal is connected in series with the negative terminal of the first DC power supply; a floating capacitor that is charged by the first DC power supply or the second DC power supply; and a half-bridge inverter module that outputs five mutually different voltage levels including zero; wherein either the first DC power supply or the second DC power supply provides power for the half-bridge inverter module; or either the first DC power supply or the second DC power supply added algebraically to the floating capacitor provides power for the half-bridge inverter module.

In some embodiments, the five-level topology unit further comprises a first switching circuit branch and a second switching circuit branch; wherein the first terminal of the first switching circuit branch is connected with the positive terminal of the first DC power supply; the second terminal of the first switching circuit branch is connected with the negative terminal of the floating capacitor; the first terminal of the second switching circuit branch is connected with the positive terminal of the floating capacitor; the second terminal of the second switching circuit branch is connected with the negative terminal of the second DC power supply.

In some embodiments, the first switching circuit branch comprises a first bidirectional switch and the second switching circuit branch comprises a second bidirectional switch; wherein the first terminal of the first bidirectional switch is connected with the first terminal of the first switching circuit branch; the second terminal of the first bidirectional switch is connected with the second terminal of the first switching circuit branch; the first terminal of the second bidirectional switch is connected with the first terminal of the second switching circuit branch; the second terminal of the second bidirectional switch is connected with the second terminal of the second switching circuit branch.

In some embodiments, the five-level topology unit further comprises a circuit module that charges the floating capacitor; wherein the circuit module comprises a first terminal, a second terminal, a third terminal, a first subordinate switching circuit branch and a second subordinate switching circuit branch; the first terminal is connected with the common terminal of the first DC power supply and the second DC power supply; the second terminal is connected with the positive terminal of the floating capacitor; the third terminal is connected with the negative terminal of the floating capacitor; two terminals of the first subordinate switching circuit branch are connected respectively with the first terminal and the second terminal of the circuit module; the second subordinate switching circuit branch is located between the first terminal and the third terminal of the circuit module.

In some embodiments, the circuit module further comprises a first inductor that connects the first terminal of the circuit module to the common terminal of the first subordinate switching circuit branch and the second subordinate switching circuit branch; and the half-bridge inverter module is connected with AC utility through a second inductor; wherein the first inductor shares a magnetic core with the second inductor.

In some embodiments, the half-bridge inverter module comprises a first subordinate module and a second subordinate module; wherein the first subordinate module comprises a first input terminal, a second input terminal, a common output terminal to the second subordinate module, a first switching circuit sub-branch and a second switching circuit sub-branch; the second subordinate module comprises a third input terminal, a fourth input terminal, the common output terminal (that is also the output terminal of the half-bridge inverter module), a third switching circuit sub-branch and a fourth switching circuit sub-branch; the first input terminal is connected with the positive terminal of the first DC power supply; the second input terminal is connected with the positive terminal of the floating capacitor; the third input terminal is connected with the negative terminal of the floating capacitor; the fourth input terminal is connected with the negative terminal of the second DC power supply; there is the first switching circuit sub-branch between the first input terminal and the output terminal; there is the second switching circuit sub-branch between the second input terminal and the output terminal; there is the third switching circuit sub-branch between the third input terminal and the output terminal; there is the fourth switching circuit sub-branch between the fourth input terminal and the output terminal; the output terminal is used as an alternating current terminal.

Provided herein is a single phase five-level inverter.

The said single phase five-level inverter comprises at least a controller and the said five-level topology unit. The controller provides a control signal for each bidirectional switch in the five-level topology unit so that each one is driven by its own control signal.

In some embodiments, one terminal of AC utility is connected with the common terminal of the first DC power supply and the second DC power supply while the other terminal of AC utility is connected with the half-bridge inverter module.

Also provided herein is a three-phase five-level inverter.

The said three-phase-five-level inverter comprises at least a controller and three of the said five-level topology units. The said three five-level topology units share the said first DC power supply and second DC power supply. All the first input terminals of the first subordinate modules in the three five-level topology units are connected with the positive terminal of the first DC power supply; all the first terminals of the circuit modules in the three five-level topology units are connected with the common terminal of the first DC power supply and the second DC power supply; all the fourth input terminals of the second subordinate modules in the three five-level topology units are connected with the negative terminal of the second DC power supply; all the output terminals of the half-bridge inverter modules in the three five-level topology units are connected respectively with the three phase terminals of AC utility. The controller provides a control signal for each bidirectional switch in the three five-level topology units so that it is driven by its own control signal.

In some embodiments, all the circuit modules in the three five -level topology units of the three-phase five-level inverter share the first inductor.

In some embodiments, the common terminal of the first DC power supply and the second DC power supply of the three-phase five-level inverter is connected with the neutral terminal of AC utility.

Consequently, provided in the invention are five-level topology units and inverter thereof without an extra boosting circuit wherein the cost is reduced by using only one AC filtering inductor and high efficiency is achieved tor the absence of the extra boosting circuit and, furthermore, wherein the leakage current is eliminated substantially by using the half-bridge inverter module. The five-level inverter including the said five-level topology unit without an extra circuit to raise input voltage (i.e. Boost circuit) is able to output the same AC power as the said five-level full bridge inverter under the same working condition.

In addition, the time for both charging and discharging the floating capacitor is equal to the switching period of the semiconductor switch in the five-level topology units. It is usually fifty microseconds in practical situation. It is so short that the said floating capacitor with small capacity is able to meet the requirement.

The five-level topology units and inverter thereof provided in the invention can be used for, but not limited to, renewable energy power system, such as single-phase or three-phase grid-connected photovoltaic system.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, reference is now made to the following description taken in conjunction with accompanying drawings, in which:

FIG. 1 is a circuit diagram in partial block form of a five-level inverter according to an embodiment of the invention.

FIG. 2 is another circuit diagram in partial block form of a five-level inverter according to an embodiment of the invention.

FIG. 3 is the first schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 4 is the second schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 5 is the third schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 6 is the fourth schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 7 is the fifth schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 8 is the sixth schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 9 is the seventh schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 10 is the eighth schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 11 is the ninth schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 12 is the tenth schematic circuit diagram of the circuit module according to en embodiment of the invention.

FIG. 13 is the eleventh schematic circuit diagram of the circuit module according to an embodiment of the invention.

FIG. 14 is the twelfth schematic circuit diagram of the circuit module according to an embodiment of the invention,

FIG. 15 is the first schematic circuit diagram of the said first subordinate module according to an embodiment of the invention.

FIG. 16 is the second schematic circuit diagram of the said first subordinate module according to an embodiment of the invention.

FIG. 17 is the third schematic circuit diagram of the said first subordinate module according to an embodiment of the invention.

FIG. 18 is the first schematic circuit diagram of the said second subordinate module according to an embodiment of the invention.

FIG. 19 is the second schematic circuit diagram of the said second subordinate module according to an embodiment of the invention.

FIG. 20 is the third schematic circuit diagram of the said second subordinate module according to an embodiment of the invention.

FIG. 21 is the first schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 22 is the second schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 23 is the third schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 24 is the fourth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 25 is the fifth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 26 is the sixth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 27 is the seventh schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 28 is the eighth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 29 is the ninth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 30 is the tenth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 31 is the eleventh schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 32 is the twelfth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 33 is the thirteenth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 34 is the fourteenth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 35 is the fifteenth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 36 is the sixteenth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 37 is the seventeenth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 38 is the eighteenth schematic circuit diagram of the half-bridge inverter module according to an embodiment of the invention.

FIG. 39 is the nineteenth schematic circuit diagram of the half bridge inverter module according to an embodiment of the invention.

FIG. 40 is the twentieth schematic circuit diagram of the half-bridge inverter module according to en embodiment of the invention.

FIG. 41 is the schematic circuit diagram of a single phase five-level inverter according to an embodiment of the invention.

FIG. 42 is the first working mode diagram of a single phase five-level inverter according to an embodiment of the invention.

FIG. 43 is the second working mode diagram of a single phase five-level inverter according to art embodiment of the invention.

FIG. 44 is the third working mode diagram of a single phase five-level inverter according to an embodiment of the invention.

FIG. 45 is the fourth working mode diagram of a single phase five-level inverter according to an embodiment of the invention.

FIG. 46 is the fifth working mode diagram of a single phase five-level inverter according to an embodiment of the invention.

FIG. 47 is the sixth working mode diagram of a single phase five-level inverter according to an embodiment of the invention.

FIG. 48 is the first modulation mode diagram of a five-level inverter according to an embodiment of the invention.

FIG. 49 is the second modulation mode diagram of a five-level inverter according to an embodiment of the invention.

FIG. 50 is the third modulation mode diagram of a five-level inverter according to an embodiment of the invention.

FIG. 51 is an equivalent block diagram of a single phase five-level inverter according to an embodiment of the invention.

FIG. 52 is the first equivalent block diagram of a three-phase five-level inverter according to an embodiment of the invention.

FIG. 53 is the second equivalent block diagram of a three-phase five-level inverter according to an embodiment of the invention.

FIG. 54 is the third equivalent block diagram of a three-phase five-level inverter according to an embodiment of the invention.

FIG. 55 is the fourth equivalent Mock diagram of a three-phase five-level inverter according to an embodiment of the invention.

For convenience in description, identical component's have been given the same reference numbers in the various drawings.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Provided herein are five-level topology units and inverter thereof, for a better understanding of the invention, and to show more clearly bow it may be carried into effect, embodiments will be described in detail with reference of the accompanying drawings. Of course, the embodiments described below are part of the invention examples, not all of them. Those skilled in the art will recognize or be able to ascertain variants of the embodiments described herein. Such variants are within the scope of the invention and are covered by the appended claims.

As shown in FIG. 1, the term “PW” as used herein is intended to refer to photovoltaic arrays (i.e. DC power supply), U_(PV) is its DC output voltage, M1 is the said circuit module in the five-level topology unit, M2 is the said half-bridge inverter module, C₁ is a first capacitor (i.e. the first DC power supply), C₂ is a second capacitor the second DC power supply) and C_(s) is the boating capacitor. The said first switching circuit branch comprises a bidirectional switch T₁ and the said second switching circuit branch comprises a bidirectional switch T₂.

Of course, the PV is able to he replaced by the other DC power supply. That is to say, the DC power supply is not limited to PV in the invention.

Notice that diodes are used for the elements characterised by single directional conduction in the invention, but not limited to diodes. The positive terminal of diode is referred to Anode and the negative terminal is Cathode.

The kind of switch MOSFET is used for the said semiconductor switch in the invention. Take the N-channel MOSFET for example. The first terminal of N-channel MOSFET is referred to Drain, the second terminal is Source and the control terminal is Gate. The control terminal of each semiconductor switch in the said five-level topology unit is provided with its owe control signal, for the sake of brevity, it is not described repeatedly below.

To make sure the current in the branch of each semiconductor switch located flows in both directions, each semiconductor switch in the invention is reversely parallel connected with a diode. For the sake of brevity, the term “bidirectional switch” as used herein is intended to refer to a semiconductor switch connected in reverse parallel with a diode.

The said semiconductor switch can also be implemented by the other kind of transistor, for example, the NPN type transistor. For the NPN type transistor, the first terminal is referred to Collector terminal, the second terminal is Emitter and the control terminal is Base. Of course, the semiconductor switch is not limited to MOSFET or the NPN type transistor. That is to say, the other triode with characteristics of alternative states (on and off) is able to be used as the said semiconductor switch in the invention.

The negative terminal of the said first capacitor C₁ is connected with the positive of the said second C₂, and the positive of the said first capacitor C₂ is connected with the positive of the said PV. The negative terminal of the said second capacitor C₂ is connected with the negative of the said PV.

The said circuit module M1 at least comprises a first terminal X, a second terminal A, a third terminal B, a first subordinate switching circuit branch and a second subordinate switching circuit branch. The two terminals of the first subordinate switching circuit branch are connected respectively with the said first terminal X and the said second terminal A. The second subordinate switching circuit branch is located between the said first terminal X and the said third terminal B. The said first terminal X is connected with the common terminal of the said first capacitor C₁ and the said second C₂. The said second terminal A is connected with the positive terminal of the said floating capacitor C_(s) and the said third terminal B is connected with the negative terminal of the said floating capacitor C_(s).

The said half-bridge inverter module M2 at least comprises a first input terminal I1, a second input terminal I2, a third input terminal I3, a fourth input terminal I4, an output terminal O and four switching circuit sub-branches. There is a switching circuit sub-branch between each of the said input terminals and the said output terminal O. The said output terminal O is connected with the AC utility.

As shown in FIG. 2, the said half-bridge inverter module M2 is divided into two subordinate modules. They are the first subordinate module M21 and the second subordinate module M22. The first subordinate module M21 comprises the first input terminal I1, the second input terminal I2, the output terminal O, the said first switching circuit sub-branch and the said second one. The second subordinate module M22 comprises the third input terminal I3, the fourth input terminal I4, the output terminal O, the said third switching circuit sub-branch and the said fourth one.

The first terminal of the said bidirectional switch I1 is connected with both the said first input terminal I1 of the said half-bridge inverter module M2 and the positive terminal of the said first capacitor C₁. The second terminal of the said bidirectional switch T1 is connected with the said third input terminal I3. The first terminal of the said bidirectional switch T2 is connected with the said second input terminal I2 and its second terminal is connected with both the said fourth input terminal I4 and the negative terminal of the said second capacitor C₂.

The positive terminal of the said floating capacitor C_(s) is connected with the said second input terminal I2 of the said half-bridge inverter module M2, and its negative terminal is connected with the said third input terminal I3. The said floating capacitor C_(s) is mainly used to increase input voltage of inverter.

The said circuit module M1 is mainly used to charge the said floating capacitor C_(s) by alternative loop circuits. The first loop circuit comprises the said first capacitor C₁, the circuit branch formed by I1 and I2, the said floating capacitor C_(s) and the said second subordinate switching circuit branch in said circuit module M1. The second loop circuit comprises the said second capacitor C₂, the said first subordinate switching circuit branch, the said floating capacitor C_(s), and the circuit branch formed by I3 and I4. The floating capacitor C_(s) is discharged when it acts as part of the DC power supply of inverter.

The sum time for both charging and discharging the floating capacitor C_(s) is equal to the switching period of the semiconductor switch in the inverter. It is usually 50 microseconds in practical situation, it is so short that the floating capacitor C_(s) voltage change caused by charging and discharging it can be completely neglected. So the said floating capacitor with small capacity is able to meet the requirement. The period of the said capacitor C₁ or C₂ charged and discharged is the same with that of industrial power if the input power is drawn from utility. So there is in need of the said capacitor C₁ or C₂ with large capacity. In practical situation, the capacity of the said capacitor C₁ or C₂ usually hundreds of times of that of the floating capacitor C_(s).

It is easy to find that the said floating capacitor C_(s) voltage equals the said first capacitor C₂ voltage or the sale second capacitor C₂ voltage by controlling either of the on end off states of each semiconductor switch in the said five-level topology unit.

Suppose the capacity of the first capacitor C₁ is equal to that of the second C₂ according to the embodiment. Of course, in the invention it is not limited to the relationships in value of the capacity of the first capacitor C₂ and that of the second C₂. So both the said first capacitor C₂ voltage and the said second C₂ voltage are half of U_(PV). The said floating capacitor C_(s) voltage is also half of U_(PV).

According to the embodiment, either the first capacitor C₁ or the second C₂ provides power for the half-bridge inverter module M2, or either the first capacitor C₁ or the second C₂ added algebraically to the floating capacitor C_(s) provides power for the half-bridge inverter module M2. In the latter case, the input voltage of the half-bridge inverter module M2 is U_(PV) which is the same with that of the full bridge inverter under the same working condition.

Therefore, the five-level inverter including the said five-level topology unit without an extra circuit to raise input voltage (i.e. Boost circuit) is able to output the same AC power as the said five-level full bridge inverter under the same working condition. As the absence of the Boost circuit, the said five-level inverter achieves low cost, high efficiency and reliability. In addition, the cost is reduced by using only one AC filtering inductor and the leakage current is eliminated substantially by using the half-bridge inverter module.

It can be used for, but not limited to, renewable energy power system, such as single-phase or three-phase grid-connected photovoltaic system.

FIG. 3 shows the first schematic circuit diagram of the said circuit module M1 according to an embodiment of the invention. The said circuit module M1 comprises a first bidirectional switch T₃₂, a second bidirectional switch T₃₂, a first diode D₃₁ and a second diode D₃₂.

The positive terminal of the first diode D₃₂ is connected with the negative terminal of the second diode D₃₂ and the negative terminal of the first diode D₃₁ is connected with the first terminal of the first bidirectional switch T₃₁. The second terminal of the first bidirectional switch T₃₁ is connected with the said second terminal A of the said circuit module M1. The positive terminal of the second diode D₃₂ is connected with the second terminal of the second bidirectional switch T₃₂ whose first terminal is connected with the said third terminal B. The common terminal of the first diode D₃₁ end the second diode D₃₂ is connected with the said first terminal X.

The said first subordinate switching circuit branch in the said circuit module M1 comprises the first diode D₃₁ and the first bidirectional switch T₃₁.The said second subordinate switching circuit branch comprises the second diode D₃₂ the second bidirectional switch T₃₂.

FIG. 4 is the second schematic circuit diagram of the said circuit module M1 according to an embodiment of the invention. It can be seen that in FIG. 4 there is an extra first inductor L₁ between the said first terminal X and the common terminal of the first diode D₃₁ and the second diode D₃₂ based on the circuit in FIG. 3. The extra first inductor L₁ is used to prevent impact current in the said charging loop circuit from influencing the said floating capacitor C_(s). Similarly, the first inductor L₁ respectively in any one of the circuits in FIG. 6, FIG. 8 and FIG. 10 acts as the same role. For the sake of brevity, it is not described repeatedly below.

As the capacity of the said floating capacitor C_(s) is very small, the first inductor L₁ with small inductance is able to meet the requirement. In practical situation, the second inductance L₂ is usually hundreds of times of the inductance L₁. To reduce in size and lower cost, the inductor L₁ able to share a magnetic core with the second inductor L₂.

FIG. 5 is the third schematic circuit diagram of the said circuit module M1 according to an embodiment of the invention. The said circuit module M1 comprises a first bidirectional switch T₅₁, a first diode D₅₁, a second diode D₅₂, a third diode D₅₃, and a fourth diode D₅₄.

The positive terminal of the first diode D₅₁ is connected with the said first terminal X and its negative terminal is connected with the first terminal of the first bidirectional switch T₅₁. The negative terminal of the third diode D₅₃ is connected with the negative of the first diode D₅₁, and its positive terminal is connected with the said third terminal B. The negative terminal of the second diode D₅₂ is connected with the positive terminal of the first diode D₅₁, and its positive terminal is connected with the second terminal of the first bidirectional switch T₅₁. At the same time, the negative terminal of the fourth diode D₅₄ is connected with the said second terminal A, and its positive terminal is connected with the positive terminal of the second diode D₅₂.

The said first subordinate switching circuit branch in the said circuit module M1 comprises the first diode D₅₂, the fourth diode D₅₄ and the first bidirectional switch T₅₁. The said second subordinate switching circuit branch comprises the second diode D₅₂, the third diode D₅₃ and the first bidirectional switch T₅₁.

FIG. 7 is the fifth schematic circuit diagram of the said circuit module M1 according to an embodiment of the invention. The said circuit module M1 comprises a first bidirectional switch T₇₁, a second bidirectional switch T₇₂, a third bidirectional switch T₇₃ and a fourth bidirectional switch T₇₄.

The second terminal of the first bidirectional switch T₇₁ is connected with the first terminal of the second bidirectional switch T₇₂, and its first terminal is connected with the first terminal of the third bidirectional switch T₇₃ whose second is connected with the said second terminal A. The common terminal of the first bidirectional switch T₇₁ and the second bidirectional switch T₇₂ is connected with the said first terminal X. At the same time, the second terminal of the second bidirectional switch T₇₂ is connected with the second terminal of the fourth bidirectional switch T₇₄ whose first terminal is connected with the said third terminal B.

The said first subordinate switching circuit branch in the said circuit module M1 comprises the first bidirectional switch T₇₁ and the third bidirectional switch T₇₃. The said second subordinate switching circuit branch comprises the second bidirectional switch T₇₂ and the fourth bidirectional switch T₇₄.

FIG. 9 is the seventh schematic circuit diagram of the said circuit module M1 according to an embodiment of the invention. The said circuit module M1 comprises a first bidirectional switch T₉₁, a second bidirectional switch T₉₂, a first diode D₉₁˜eighth diode D₉₈.

The positive terminal of the first diode D₉₁ is connected with the negative terminal of the second diode D₉₂ and the negative of the first diode D₉₁ connected with the first terminal of the first bidirectional switch T₉₁. The positive terminal of the second diode D₉₂ is connected with the second terminal of the first bidirectional switch T₉₁. The common terminal of the first diode D₉₁ and the second diode D₉₂ is connected with the said first terminal X.

The positive terminal of the third diode D₉₃ connected with the negative terminal of the fourth diode D₉₄ and the negative of the third diode D₉₃ is connected with the first terminal of the first bidirectional switch T₉₁. The positive terminal of the fourth diode D₉₄ is connected with the second terminal of the first bidirectional switch T₉₁. The common terminal of the third diode D₉₃ and the fourth diode D₉₄ is connected with the said second terminal A.

The positive terminal of the fifth diode D₉₅ is connected with the negative terminal of the sixth diode D₉₆. The negative terminal of the fifth diode D₉₅ is connected with the first terminal of the second bidirectional switch T₉₂. The positive terminal of the sixth diode D₉₆ is connected with the second terminal of the second bidirectional switch T₉₂. The common terminal of the fifth diode D₉₅ the sixth diode D₉₆ is connected with the first terminal X.

The positive terminal of the seventh diode D₉₇ is connected with the negative terminal of the eighth diode D₉₈. The negative of the seventh diode D₉₇ is connected with the first terminal of the second bidirectional switch T₉₂. The positive terminal of the eighth diode D₉₈ is connected with the second terminal of the second bidirectional switch T₉₂. The common terminal of the seventh diode D₉₇ and the eighth diode D₉₈ is connected with the third terminal B.

The said first subordinate switching circuit branch in the said circuit module M1 comprises the first bidirectional switch T₉₁, the first diode D₉₁ and the fourth diode D₉₄, or comprises the first bidirectional switch T₉₁, the second diode D₉₂ and the third diode D₉₃. The said second subordinate switching circuit branch comprises the second bidirectional switch T₉₂, the fifth diode D₉₅ and the eighth diode D₉₈, or comprises the second bidirectional switch T₉₂, the sixth diode D₉₆ and the seventh diode D₉₇.

FIG. 11 is the ninth schematic circuit diagram of the said circuit module M1 according to an embodiment of the invention. The said circuit module M1 comprises an extra third bidirectional switch T₁₁₃ and a fourth bidirectional switch T₁₁₄ based on the circuit in FIG. 4.

As shown in FIG. 11, the first terminal of the third bidirectional switch T₁₁₃ is connected with the negative terminal of the first diode D₃₁, and the second terminal of the third bidirectional switch T₁₁₃ is connected with the first terminal of the fourth bidirectional switch T₁₁₄ whose second terminal is connected with the positive terminal of the second diode D₃₂. The common terminal of the third bidirectional switch T₁₁₃ and the fourth bidirectional switch T₁₁₄ is connected with the said first terminal X.

The said first subordinate switching circuit branch in the said circuit module M1 comprises the first diode D₃₁, the first bidirectional switch T₃₁ and the first inductor L₁. The said second subordinate switching circuit branch comprises the second bidirectional switch T₃₂,the second diode D₃₂ and the first inductor L₁. The third bidirectional switch T₁₂₃ and the fourth bidirectional switch T₁₂₄ are used to provide a freewheeling branch for the current in the first inductor L₁.

FIG. 12 is the tenth schematic circuit diagram of the said circuit module M1 according to an embodiment of the invention. The said circuit module M1 comprises an extra fifth bidirectional switch T₁₂₅ and a sixth bidirectional switch T₁₂₆ based on the circuit in FIG. 8. The fifth bidirectional switch T₁₂₅ and the sixth bidirectional switch T₁₂₆ are used to provide a freewheeling branch for the current in the first inductor L₁.

As shown in FIG. 12, the first terminal of the fifth bidirectional T₁₂₅ switch connected with that of the first bidirectional switch T₇₁ and the second terminal is connected with the said first terminal X. The first terminal of the sixth bidirectional switch T₂₂₆ is connected with the said first terminal X and the second terminal is connected with that of the second bidirectional switch T₇₂.

The said first subordinate switching circuit branch of the said circuit module M1 comprises the first inductor L₁, the first bidirectional switch T₇₁ and the third bidirectional switch T₇₃. The said second subordinate switching circuit branch comprises the first inductor L₁, the second bidirectional switch T₇₂ and the fourth bidirectional switch T₇₃.

FIG. 13 is the eleventh schematic circuit diagram of the said circuit module M1 according to an embodiment of the invention. The said circuit module M1 comprises an extra third bidirectional switch T₁₃₃ and a fourth bidirectional switch T₁₃₄ in contrast with the circuit in FIG. 10. The third bidirectional switch T₁₃₃ and the fourth bidirectional switch T₁₃₄ are used to provide a freewheeling branch for the current in the first inductor L₁.

The first terminal of the third bidirectional switch T₂₃₃ is connected with that of the first bidirectional switch T₉₁, and the second terminal is connected with the said first terminal X. The first terminal of the fourth bidirectional switch T₁₃₄ is connected with the said first terminal X and the second terminal is connected with that of the second bidirectional switch T₉₂.

The said first subordinate switching circuit branch of the said circuit module M1 comprises the first inductor L₁, the first bidirectional switch T₉₁, the first diode D₉₁ the fourth diode D₉₄ or comprises the first inductor L₁, the first bidirectional switch T₉₁, the second diode D₉₂ and the third diode D₉₃. The said second subordinate switching circuit branch comprises the first inductor L₁, the second bidirectional switch T₉₂, the fifth diode D₉₅ and the eighth diode D₉₈ or comprises the first inductor L₁, the second bidirectional switch T₉₂, the sixth diode D₉₆ and the seventh diode D₉₇.

FIG. 14 is the twelfth schematic circuit diagram of the said circuit module M1 according to an embodiment of the invention. The said circuit module M1 comprises an extra second bidirectional switch T₁₄₂ and a third bidirectional switch T₁₄₃ in contrast with the circuit in FIG. 6.

The first terminal of the second bidirectional switch T₁₄₂ is connected with that of the first bidirectional switch T₅₁ and the second terminal is connected with the said first terminal X. The first terminal of the third bidirectional switch T₁₄₃ connected with the said first terminal X and the second terminal is connected with that of the first bidirectional switch T₅₁.

The said first subordinate switching circuit branch in the said circuit module M1 comprises the first inductor L₁, the first diode D₅₁, the fourth diode D₅₄ and the first bidirectional switch T₅₁. The said second subordinate switching circuit branch comprises the first inductor L₁, the second diode D₅₂, the third diode D₅₃ and the first bidirectional switch T₅₁. The second bidirectional switch T₁₄₂ and third bidirectional switch T₁₄₃ are used to provide a freewheeling branch for the current in the first inductor L₁.

Provided are three kinds of circuits for the said fist subordinate module M21 in the said half-bridge inverter module M2.

FIG. 15 is the first schematic circuit diagram of the said first subordinate module M21 according to an embodiment of the invention. The said first subordinate module M21 comprises a first bidirectional switch T₁₅₁, a second bidirectional switch T₁₅₂ a first diode D₁.

The positive terminal of the first diode D₁ is connected with the said first input terminal I1 of the said half-bridge inverter module M2 and the negative terminal is connected with the first terminal of the first bidirectional switch T₁₅₁ whose second terminal is connected with the first of the second bidirectional switch T₁₅₂. The common terminal of the first bidirectional switch T₁₅₁ and the second bidirectional switch T₁₅₂ is connected with the said second input terminal I2. The second terminal of the second bidirectional switch T₁₅₂ is connected with the output terminal O.

FIG. 16 is the second schematic circuit diagram of the said first subordinate module M21 according to an embodiment of the invention. The said first subordinate module M21 comprises a first bidirectional switch T₁₈₁, a second bidirectional switch T₁₈₂ and a first diode D₁.

The positive terminal of the first diode D₁ is connected with the said first input terminal I1 and the negative terminal is connected with the first terminal of the first bidirectional switch T₁₆₁ whose second terminal is connected with the output terminal O. At the same time, the first terminal of the second bidirectional switch T₁₆₂ is connected with the said second input terminal I2 and the second terminal is connected with the output terminal O.

FIG. 17 is the third schematic circuit diagram of the said first subordinate module M21 according to an embodiment of the invention. The said first subordinate module M21 comprises a first bidirectional switch T₂₇₁, a second bidirectional switch T₂₇₂ and a first diode D₁.

The positive terminal of the first diode D₁ is connected with the said first input terminal I1 and the negative terminal is connected with the first terminal of the second bidirectional switch T₁₇₂ whose second terminal is connected with the output terminal O. The first terminal of the second bidirectional switch T₂₇₂ is connected with the second of the first bidirectional switch T₂₇₁ whose first terminal is connected with the said second input terminal I2.

Provided below are three kinds of circuits for the said second subordinate module M22 in the said half-bridge inverter module M2.

FIG. 18 is the first schematic circuit diagram of the said second subordinate module M22 according to an embodiment of the invention. The said second subordinate module M22 comprises a third bidirectional switch T₁₈₃, a fourth bidirectional switch T₁₈₄ a second diode D₂.

The first terminal of the third bidirectional switch T₁₈₃ is connected with the output terminal O and the second terminal is connected with the said third input terminal I3. The first terminal of the fourth bidirectional switch T₁₈₄ is connected with the second of the third bidirectional switch T₁₈₃ and the second terminal is connected with the positive terminal of the second diode D₂. The negative terminal of the second diode D₂ is connected with the said fourth input terminal I4.

FIG. 19 is the second schematic circuit diagram of the said second subordinate module M22 according to an embodiment of the invention. The said second subordinate module M22 comprises a third bidirectional switch T₁₉₃, a fourth bidirectional switch T₁₉₄ and a second diode D₂.

The first terminal of the third bidirectional switch T₁₉₃ is connected with the output terminal O and the second terminal is connected with the said third input terminal I3. The first terminal of the fourth bidirectional switch T₁₉₄ is connected with the output terminal O end the second terminal is connected with the positive terminal of the second diode D₂. The negative terminal of the second diode D₂ is connected with the said fourth input terminal I4.

FIG. 20 is the third schematic circuit diagram of the said second subordinate module M22 according to an embodiment of the invention. The said second subordinate module M22 comprises a third bidirectional switch T₂₀₃, a fourth bidirectional switch T₂₀₄ and a second diode D₂.

The first terminal of the third bidirectional switch is connected with the output terminal O and the second terminal is connected with both the first terminal of the fourth bidirectional switch T₂₀₄ and the positive terminal of the second diode D₂. The second terminal of the fourth bidirectional switch T₂₀₄ is connected with the said third input terminal I3. The negative terminal of the second diode D₂ is connected with the said fourth input terminal I4.

The said half-bridge inverter module M1 includes any one of the said three kinds of the said first subordinate module M21, and any one of the said three kinds of the said second subordinate module M22.

For example, FIG. 21 is the first schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention, it consists of the circuits in both FIG. 15 and FIG. 18. It comprises the first diode D₁, the second diode D₂, the first bidirectional switch T₁₅₁, the second bidirectional switch T₁₅₂, the third bidirectional switch T₁₈₃ and the fourth bidirectional switch T₁₈₄.

The first switching circuit sub-branch of the said half-bridge inverter module M2 comprises the first diode D₁, the first bidirectional switch T₁₅₁ and the second bidirectional switch T₁₅₂. The second switching circuit sub-branch comprises the second bidirectional switch T₁₅₂. The third switching circuit sub-branch comprises the third bidirectional switch T₁₈₃. The fourth switching circuit sub-branch comprises the second diode D₂, the third bidirectional switch T₁₈₃ and the fourth bidirectional switch T₁₈₄.

FIG. 22 is the second schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention. It can be seen that a ninth bidirectional switch T₉ and a tenth bidirectional switch T₁₀ are used to replace respectively the first diode D₁ and the second diode D₂ in the circuit in FIG. 21 to make sure the current flows in both directions.

The first terminal of the ninth bidirectional switch T₉ is connected with the first of the first bidirectional switch T₁₅₁, and the second terminal of the ninth bidirectional switch T₉ is connected with the said first input terminal I1. The first terminal of the tenth bidirectional switch T₁₀ is connected with the said fourth input terminal I4 and the second terminal of the tenth bidirectional switch T₁₀ is connected with the second of the fourth bidirectional switch T₁₅₄.

Similarly, the ninth bidirectional switch T₉ and the tenth bidirectional switch T₁₀ in any one of the circuits respectively in FIG. 24, FIG. 26, FIG. 28, FIG. 30, FIG. 32, FIG. 34, FIG. 36 and FIG. 38 act as the same role. For the sake of brevity, it is not described repeatedly below.

FIG. 23 is the third schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention. It consists of the circuits in both FIG. 16 and FIG. 19. It comprises the first diode D₁, the second diode D₂, the first bidirectional switch T₁₆₁, the second bidirectional switch T₁₆₂, the third bidirectional switch T₂₉₃ and the fourth bidirectional switch T₂₉₄.

The first switching circuit sub-branch comprises the first diode and the first bidirectional switch T₂₆₁. The second switching circuit sub-branch comprises the second bidirectional switch T₂₆₂. The third switching circuit sub-branch comprises the third bidirectional switch T₁₉₃. The fourth switching circuit sub-branch comprises the second diode D₂ and the fourth bidirectional switch T₁₉₄.

FIG. 25 is the fifth schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention, it consists of the circuits in both FIG. 17 and FIG. 20. It comprises the first diode D₁, the second diode D₂, the first bidirectional switch T₁₇₁, the second bidirectional switch T₁₇₂, the third bidirectional switch T₂₀₃ and the fourth bidirectional switch T₂₀₄.

The first switching circuit sub-branch comprises the first diode D₁ and the second bidirectional switch T₁₇₂. The second switching circuit sub-branch comprises the first bidirectional switch T₁₇₁ and the second bidirectional switch T₁₇₂. The third switching circuit sub-branch comprises the third bidirectional switch T₂₀₃ and the fourth bidirectional switch T₂₀₄. The fourth switching circuit sub-branch comprises the second diode D₂ and the third bidirectional switch T₂₀₃.

FIG. 27 is the seventh schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention. It consists of the circuits in both FIG. 15 and FIG. 20. It comprises the first diode D₁, the second diode D₂, the first bidirectional switch T₁₅₁, the second bidirectional switch T₁₅₂, the third bidirectional switch T₂₀₃ and the fourth bidirectional switch T₂₀₄.

The first switching circuit sub-branch comprises the first diode D₁, the first bidirectional switch T₁₅₁ and the second bidirectional switch T₁₅₂. The second switching circuit sub-branch comprises the second bidirectional switch T₁₅₂. The third switching circuit sub-branch comprises the third bidirectional switch T₂₀₃ and the fourth bidirectional switch T₂₀₄. The fourth switching circuit sub-branch comprises the second diode D₂ and the third bidirectional switch T₂₀₃. It is easy to make a similar analysis to the circuits in figures at the back. For the sake of brevity, it is not described repeatedly below.

FIG. 29 is the ninth schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention. It consists of the circuits in both FIG. 15 and FIG. 19. It comprises the first diode D₁, the second diode D₂, the first bidirectional switch T₁₅₁, the second bidirectional switch T₁₅₂, the third bidirectional switch T₁₉₃ and the fourth bidirectional switch T₁₉₄.

FIG. 31 is the eleventh schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention. It consists of the circuits in both FIG. 16 and FIG. 20. It comprises the first diode D₁, the second diode D₂, the first bidirectional switch T₁₆₁, the second bidirectional switch T₁₆₂, the third bidirectional switch T₂₀₃ and the fourth bidirectional switch T₂₀₄.

FIG. 33 is the thirteenth schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention. It consists of the circuits in both FIG. 16 and FIG. 18. It comprises the first diode D₁, the second diode D₂, the first bidirectional switch T₁₆₁, the second bidirectional switch T₁₆₂, the third bidirectional switch T₁₈₃ and the fourth bidirectional switch T₁₈₄.

FIG. 35 is the fifteenth schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention. It consists of the circuits in both FIG. 17 and FIG. 18. It comprises the first diode D₁, the second diode D₂, the first bidirectional switch T₁₇₁, the second bidirectional switch T₁₇₂, the third bidirectional switch T₁₈₃ and the fourth bidirectional switch T₁₈₄.

FIG. 37 is the seventeenth schematic circuit diagram of the said half-bridge inverter module M1 according to an embodiment of the invention. It consists of the circuits in both FIG. 17 and FIG. 19. It comprises the first diode D₁, the second diode D₂, the first bidirectional switch T₁₇₁, second bidirectional switch T₁₇₂, the third bidirectional switch T₁₉₃ and the fourth bidirectional switch T₁₉₄.

FIG. 39 is the nineteenth schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention, it comprises a first diode D₃₉₁˜an eighth diode D₃₉₈ and a first bidirectional switch T₃₉₁˜fourth bidirectional switch T₃₉₄.

The positive terminal of the first diode D₃₉₁ is connected with the negative of the second diode D₃₉₂. The negative terminal of the first diode D₃₉₁ is connected with the first terminal of the first bidirectional switch T₃₉₁. The positive terminal of the second diode D₃₉₂ is connected with the second terminal of the first bidirectional switch T₃₉₁. The common terminal of the first diode D₃₉₂ and the second diode D₃₉₂ is connected with the said first input terminal I1.

The negative terminal of the third diode D₃₉₃ is connected with the first terminal of the first bidirectional switch T₃₉₁ and the positive terminal is connected with the negative of the fourth diode D₃₉₄ whose positive terminal is connected with the second terminal of the first bidirectional switch T₃₉₁. The common terminal of the third diode D₃₉₃ and fourth diode D₃₉₄ is connected with both the first terminal of the second bidirectional switch T₃₉₂ and the said second input terminal I2. The second terminal of the second bidirectional switch T₃₉₂ is connected with both the first terminal of the third bidirectional switch T₃₉₃ and the output terminal O.

The negative terminal of the fifth diode D₃₉₅ is connected with the first terminal of the fourth bidirectional switch T₃₉₄ and the positive terminal is connected with the negative of the sixth diode D₃₉₆ whose positive terminal is connected with the second terminal of the fourth bidirectional switch T₃₉₄. The common terminal of the fifth diode D₃₉₅ and the sixth diode D₃₉₆ is connected with both the second terminal of third bidirectional switch T₃₉₃ the said third input terminal I3. The negative terminal of the seventh diode D₃₉₇ connected with the first terminal of the fourth bidirectional switch T₃₉₄ and the positive terminal is connected with the negative of the eighth diode D₃₉₈. The positive terminal of the eighth diode D₃₉₈ is connected with the second terminal of the fourth bidirectional switch T₃₉₄. The common terminal of the seventh diode D₃₉₇ and the eighth diode D₃₉₈ is connected with the said fourth input terminal I4.

The first switching circuit sub-branch comprises the first diode D₃₉₁, the first bidirectional switch T₃₉₁, the fourth diode D₃₉₄ and the second bidirectional switch T₃₉₂ or comprises the second diode D₃₉₂, the first bidirectional switch T₃₉₁, the third diode D₃₉₃ and the second bidirectional switch T₃₉₂. The second switching circuit sub-branch comprises the second bidirectional switch T₃₉₂. The third switching circuit sub-branch comprises the third bidirectional switch T₃₉₃. The fourth switching circuit sub-branch comprises the seventh diode D₃₉₇, the fourth bidirectional switch T₃₉₄, the sixth diode D₃₉₆ and the third bidirectional switch T₃₉₃ or comprises the eighth diode D₃₉₈, the fourth bidirectional switch T₃₉₄, the fifth diode D₃₉₅ and the third bidirectional switch T₃₉₃.

FIG. 40 is the twentieth schematic circuit diagram of the said half-bridge inverter module M2 according to an embodiment of the invention. It comprises a first diode D₄₀₁˜eighth diode D₈₀₈ and a first bidirectional switch T₄₀₁˜fourth bidirectional switch T₄₀₄.

The positive terminal of the first diode D₄₀₁ is connected with the negative of the second diode D₄₀₂. The negative terminal of the first diode D₄₀₁ is connected with the first terminal of the first bidirectional switch T₄₀₁. The positive terminal of the second diode D₄₀₂ is connected with the second terminal of the first bidirectional switch T₄₀₂. The common terminal of the first diode D₄₀₁ and the second diode D₄₀₂ is connected with the said first input terminal I1.

The negative terminal of the third diode D₄₀₃ is connected with the first terminal of the first bidirectional switch T₄₀₁ and the positive terminal is connected with the negative of the fourth diode D₄₀₄ whose positive terminal is connected with the second terminal of the first bidirectional switch T₄₀₁. The common terminal of the third diode D₄₀₃ and the fourth diode D₄₀₄ is connected with the output terminal O.

The negative terminal of the fifth diode D₄₀₅ is connected with the first terminal of the fourth bidirectional switch T₄₀₄ and the positive terminal is connected with the negative of the sixth diode D₄₀₆ whose positive terminal is connected with the second terminal of the fourth bidirectional switch T₄₀₄. The common terminal of the fifth diode D₄₀₅ and the sixth diode D₄₀₆ is connected with the output terminal O. The negative terminal of the seventh diode D₄₀₇ is connected with the first terminal of the fourth bidirectional switch T₄₀₄ and the positive terminal is connected with the negative of the eighth diode D₄₀₈. The positive terminal of the eighth diode D₄₀₈ is connected with the second terminal of the fourth bidirectional switch T₄₀₄. The common terminal of the seventh diode D₄₀₇ and the eighth diode D₄₀₈ is connected with the said fourth input terminal I4.

The first terminal of the second bidirectional switch T₄₀₂ is connected with the said second input terminal I2. The second terminal of the second bidirectional switch T₄₀₂ is connected with both the first terminal of the third bidirectional switch T₄₀₃ and the output terminal O. The second terminal of the third bidirectional switch T₄₀₃ is connected with the said third input terminal I3.

The first switching circuit sub-branch comprises the first diode D₄₀₁, the first bidirectional switch T₄₀₁ and the fourth diode D₄₀₄, or comprises the second diode D₄₀₂, the first bidirectional switch T₄₀₁ and the third diode D₄₀₃. The second switching circuit sub-branch comprises the second bidirectional switch T₄₀₂. The third switching circuit sub-branch comprises the third bidirectional switch t₄₀₃. The fourth switching circuit sub-branch comprises the seventh diode D₄₀₂, the fourth bidirectional switch T₄₀₄ and the sixth diode D₄₀₆, or comprises the eighth diode D₄₀₈, the fourth bidirectional switch T₄₀₄ and the fifth diode D₄₀₅.

The combination of any one of the circuits in from FIG. 3 to FIG. 14 and any one of the circuits in from FIG. 21 to FIG. 40 as well as the floating capacitor C_(s), the said first bidirectional switch T₁ and the said bidirectional switch T₂ forms a five-level topology unit according to the embodiment. It is usually used with the said first capacitor C₁ and the second C₂.

A single phase five-level inverter comprises at least a controller and the said five-level topology unit. The controller provides a control signal for each bidirectional switch in the five-level topology unit so that each one is driven by its own control signal. One terminal of AC utility is connected with the common terminal of the first DC power supply and the second DC power supply while the other terminal of AC utility is connected with the half-bridge inverter module. Take a single phase five-level inverter for example to illustrate its working modes.

FIG. 41 is the schematic circuit diagram of a single phase five-level inverter according to an embodiment of the invention. It comprises a controller and a five-level topology unit including the circuits in both FIG. 4 and FIG. 21. It is used with the said first capacitor C₁ and the second C₂.

Suppose the output DC voltage of photovoltaic arrays (i.e. DC power supply) is U_(PV). Both the said first capacitor C₁ voltage and the second C₂ are half of U_(PV) as their capacities are equal according to the embodiment. The said floating capacitor C_(s) initial voltage is half of U_(PV).The current in the filtering inductor L₂ flowing from left to right in circuits from FIG. 46 to FIG. 48 is defined as positive current and the opposite as negative current.

FIG. 42 is the first working mode diagram of the single phase five-level inverter according to an embodiment of the invention. As shown in FIG. 42, the positive current is as follows: X→C₁→P→T₁→C₅→T₆→L₂→G→X, and the negative current is: X→G→L₂→T₆→C_(s)→T₁→P→C₁→X. The output voltage U_(OX) from the inverter is the sum of the said floating capacitor C_(s) voltage and the said first capacitor C₁ voltage. That is, U_(OX)=U_(PV)/2+U_(PV)/2=U_(PV).

FIG. 43 is the second working mode diagram of the single phase five-level inverter according to an embodiment of the invention. As shown in FIG. 43, the positive current is as follows: X→C₁→P→D₁→T₅→T₆→L₂→G→X. The output voltage U_(OX) from the inverter equals the said first capacitor C₁ voltage. That is, U_(OX)=U_(PV)/2. At the same time, there is a charging loop circuit: X→C₁→P→D₁→T₅→C_(s)→T₄→D₄→L₁→X. When the said floating capacitor C_(s) voltage is less than half of U_(PV), the capacitor C_(s) is charged by the said first capacitor C₁ through the charging loop circuit so that its voltage is equal to that of the said first capacitor C₁.

To simplify the control logic and lower cost, the negative current is absent. When the diode D₁ above-mentioned is replaced by directional switch T₉, the current in the branch formed by the diode D₁ is able to flow in both directions.

FIG. 44 is the third working mode diagram of the single phase five-level inverter according to an embodiment of the invention. As shown in FIG. 44, the positive current is as follows: X→L₁→D₃→T₃→T₆→L₂→G→X, it is easy to find that the output voltage U_(OX) from the inverter equals zero. That is, U_(OX)=0. The negative current is as follows: X→G→L₂→T₆→C_(s)→T₈→D₂→C₂→X. As the voltage direction of the said second capacitor C₂ is opposite to that of the said floating capacitor c_(s), the output voltage U_(OX) from the inverter equals also zero.

When the diode D₂ above-mentioned is replaced by directional switch T₁₀, the current in the branch formed by the diode D₂ is able to flow in both directions.

FIG. 45 is the fourth working mode diagram of the single phase five-level inverter according to an embodiment of the invention. As shown in FIG. 45, the positive current is as follows: X→C₁→P→D₁→T₅→C_(s)→T₇→L₂→G→X. The voltage direction of the said second capacitor C₁ is opposite to that of the said floating capacitor C_(s), so the output voltage U_(OX) from the inverter equals zero. That is, U_(OX)=0. The negative current is as follows: X→G→L₂→T₇→T₄→D₄→L₁→X. It is easy to find that the output voltage U_(OX) from the inverter equals zero.

As the current drawn from utility grid is symmetrical in its positive and negative half cycle, the positive current and negative current during a whole cycle in both the third and the fourth working modes are equal. As a result, the average voltage of the said floating capacitor C_(s) is half of U_(PV).

FIG. 46 is the fifth working mode diagram of the single phase five-level inverter according to an embodiment of the invention. As shown in FIG. 46, the negative current is as follows: X→G→L₂→T₇→T₈→D₂→C₂→X. The output voltage U_(OX) from the inverter equals the minus voltage of the said second capacitor C₂. That is, U_(OX)=−U_(PV)/2. At the same time, there is a charging loop circuit: X→L₁→D₃→T₃→C_(s)→T₇→L₂→G→X. When the said floating capacitor C_(s) voltage is less than half of U_(PV), the capacitor C_(s) is charged by the said second capacitor C₂ through the charging loop circuit so that its voltage is equal to that of the said second capacitor C₂.

FIG. 47 is the sixth working mode diagram of the single phase five-level inverter according to an embodiment of the invention. As shown in FIG. 47, the positive current is as follows: X→C₂→N→T₂→C_(s)→T₇→L₂→G→X, and the negative current is: X→G→L₂→T₇→C_(s)→T₂→N→C₂→X. The output voltage U_(OX) from the inverter is the minus sum of the said floating capacitor C_(s) voltage and the said second capacitor C₂ voltage. That is, U_(OX)=(−U_(PV)/2)+(−U_(PV)/2)=−U_(PV).

The single phase five-level inverter works alternately among the six working modes above-mentioned by controlling either of the on and off states of each switch to output the expected voltage. For the sake of brevity, the terms “A”, “B”, “C”, “D”, and “F” as used herein are intended to respectively refer to the first the second, the third, the fourth, the fifth and the sixth working mode of the single phase five-level inverter.

Since the output voltage U_(OX) from the inverter with the positive current and negative current is zero in both the third and the fourth working modes, either of the modes works or both do alternatively in practical situation.

FIG. 48 is the first modulation mode diagram of s single phase five-level inverter according to an embodiment of the invention.

As shown in FIG. 48, it is in positive half cycle of grid power during the time period of t₁-t₂. The output voltage U_(OX) from the inverter is more then half of U_(PV) but less than U_(PV). The inverter works alternately in the first working mode A end the second B.

It is in negative half cycle of grid power during the time period of t₄-t₅. The absolute value of output voltage U_(OX) from the inverter is more than half of U_(PV) but less than U_(PV). The inverter works alternately in the fifth working mode F and the sixth F.

It is in positive half cycle of grid power during the time periods of t₀-t₂and t₂-t₃. The output voltage U_(OX) from the inverter is loss than half of U_(PV) but more than zero. The inverter works alternately among the second working mode B, the third C, the second B and the fourth D.

It is in negative half cycle of grid power during the time periods of t₃-t₄ and t₅-t₆. The absolute value of output voltage U_(OX) from the inverter is more than zero but less than half of U_(PV). The inverter works alternately among the fifth working mode E, the third C, the fifth E and the fourth D.

FIG. 49 is the second modulation mode diagram of a single phase five-level inverter according to an embodiment of the invention.

As shown in FIG. 49, it is in positive half cycle of grid power during the time period of t₁-t₂. The output voltage U_(OX) from the inverter is more than half of U_(PV) but less than U_(PV). The inverter works alternately in the first working mode A and the second B.

It is in negative half cycle of grid power during the time period of t₄-t₅. The absolute value of output voltage U_(OX) from the inverter is more than half of U_(PV) but less than U_(PV). The inverter works alternately in the fifth working mode E and the sixth F.

It is in positive half cycle of grid power during the time periods of t₀-t₁ and t₂-t₃. The output voltage U_(OX) from the inverter is less than half of U_(PV) but more than zero. The inverter works alternately in the second working mode B and the third C.

It is in negative half cycle of grid power during the time periods of t₃-t₄ and t₅-t₆. The absolute value of output voltage U_(OX) from the inverter is more than zero but less than half of U_(PV). The inverter works alternately in the fifth working mode F and the fourth D.

FIG. 50 is the third modulation mode diagram of a single phase five-level inverter according to an embodiment of the invention.

As shown in FIG. 50, it is in positive he if cycle of grid power during the time period of t₁-t₂. The output voltage U_(OX) from the inverter is more then half of U_(PV) but less then U_(PV). The inverter works alternately in the first working mode A end the second B.

It is in negative half cycle of grid power during the time period of t₄-t₅. The absolute value of output voltage U_(OX) from the inverter is more than half of U_(PV) but less than U_(PV). The inverter works alternately in the fifth working mode E and the sixth F.

It is in positive half cycle of grid power during the time periods of t₀-t₁ and t₂-t₃. The output voltage U_(DX) from the inverter is less than half of U_(PV) but more than zero. The inverter works alternately in the second working mode B and the fourth D.

It is in negative half cycle of grid power during the time periods of t₃-t₄ and t₅-t₆. The absolute value of output voltage U_(OX) from the inverter is more than zero but less than half of U_(PV). The inverter works alternately in the fifth working mode E and the third C.

Provided herein is a single phase five-level inverter comprising a controller and a five-level topology unit above-mentioned according to the embodiment of the invention. The output terminals of the said controller are connected respectively with the control terminal of each semiconductor switch in the said five-level topology unit so that each semiconductor switch is provided with its own control signal.

FIG. 51 (b) is an equivalent block diagram of a five-level topology unit in FIG. 51 (a) according to an embodiment of the invention. The combination of the said circuit module M1, the said half-bridge inverter module M2, the said first switching circuit branch, the said second switching circuit branch and the said floating capacitor C, is equivalent as a five-level topology unit M in FIG. 51 (b). The said first input terminal I1 of the said half-bridge inverter module M2, the said fourth I4 and the said first terminal X of the said circuit module M1 are all used as the input terminals of the five-level topology unit M. The output terminal O of the said half-bridge inverter module M2 is used as that of the five-level topology unit M.

FIG. 52 is the first equivalent block diagram of a three-phase five-level inverter according to an embodiment of the invention. The three-phase five-level inverter comprises a controller and three of the said five-level topology units with the common capacitor C₁ and capacitor C₂. The controller provides a control signal for each bidirectional switch in the three five-level topology units so that each bidirectional switch is driven by its own control signal The said first input terminals I1 of the three five-level topology units M are all connected with the positive terminal of the capacitor C₁. Similarly, the said fourth input terminals I4 are all connected with the negative of the capacitor C₂ and the said first terminals X of the three five-level topology units M are connected with the common terminal of the capacitor C₁ and capacitor C₂. The three output terminals O are connected respectively with the three phase terminals of AC utility.

FIG. 53 is the second equivalent block diagram of a three-phase five-level inverter according to an embodiment of the invention. The difference between the circuits in FIG. 52 and FIG. 53 is that the common terminal of the first DC power supply and the second DC power supply is connected with the neutral terminal of AC utility in the circuit of FIG. 53.

FIG. 54 is the third equivalent block diagram of a three-phase five-level inverter according to an embodiment of the invention. The difference between the circuits in FIG. 52 and FIG. 54 is that all the three five-level topology units M share the first inductor in the circuit of FIG. 54.

FIG. 55 is the fourth equivalent block diagram of a three-phase five-level inverter according to an embodiment of the invention. The difference between the circuits in FIG. 55 and FIG. 54 is that the common terminal of the first DC power supply and the second DC power supply is connected with the neutral terminal of AC utility in the circuit of FIG. 55.

Each embodiment in the part of the detailed description of the embodiments goes forward one by one. The differences among the embodiments are focused on, and it is easy to understand the same or similar among all the embodiments by making a cross-reference.

Note that the relationship terms like “first”, “second” and so on are used in the invention just to separate one thing or operation from the other and not to indicate any real relationship or sequence among them. 

1. A five-level topology unit for use with a first DC power supply end a second DC power supply whose positive terminal is connected in series with the negative terminal of the first DC power supply, the five-level topology unit comprising: a floating capacitor that is charged by the first DC power supply or the second DC power supply; and a half-bridge inverter module that outputs five mutually different voltage levels including zero; wherein either the first DC power supply or the second DC power supply provides power for the half-bridge inverter module; or either the first DC power supply or the second DC power supply added algebraically to the floating capacitor provides power for the half-bridge inverter module.
 2. A five-level topology unit, comprising: a first DC power supply and a second DC power supply whose positive terminal is connected in series with the negative terminal of the first DC power supply; a floating capacitor that is charged by the first DC power supply or the second DC power supply; and a half-bridge inverter module that outputs five mutually different voltage levels including zero; wherein either the first DC power supply or the second DC power supply provides power for the half-bridge inverter module; or either the first DC power supply or the second DC power supply added algebraically to the floating capacitor provides power for the half-bridge inverter module.
 3. The five-level topology unit of claim 1 or 2, further comprising a first switching circuit branch and a second switching circuit branch; wherein the first terminal of the first switching circuit branch is connected with the positive terminal of the first DC power supply; the second terminal of the first switching circuit branch is connected with the negative terminal of the floating capacitor; the first terminal of the second switching circuit branch is connected with the positive terminal of the floating capacitor; the second terminal of the second switching circuit branch is connected with the negative terminal of the second DC power supply.
 4. The five-level topology unit of claim 1 or 2, further comprising a circuit module that is used to charge the floating capacitor; wherein the circuit module comprises a first terminal, a second terminal, a third terminal, a first subordinate switching circuit branch and a second subordinate switching circuit branch; the first terminal is connected with the common terminal of the first DC power supply and the second DC power supply; the second terminal is connected with the positive terminal of the floating capacitor; the third terminal is connected with the negative terminal of the floating capacitor; two terminals of the first subordinate switching circuit branch are connected respectively with the first terminal and the second terminal of the circuit module; the second subordinate switching circuit branch is located between the first terminal and the third terminal of the circuit module.
 5. The five-level topology unit of claim 1 or 2, wherein the half-bridge inverter module comprises a first subordinate module and a second subordinate module; the first subordinate module comprises a first input terminal, a second input terminal, a common output terminal to the second subordinate module, a first switching circuit sub-branch and a second switching circuit sub-branch; the second subordinate module comprises a third input terminal, a fourth input terminal, the common output terminal, a third switching circuit sub-branch and a fourth switching circuit sub-branch; the first input terminal is connected with the positive terminal of the first DC power supply; the second input terminal is connected with the positive terminal of the floating capacitor; the third input terminal is connected with the negative terminal of the floating capacitor; the fourth input terminal is connected with the negative terminal of the second DC power supply; there is the first switching circuit sub-branch between the first input terminal and the output terminal; there is the second switching circuit sub-branch between the second input terminal and the output terminal; there is the third switching circuit sub-branch between the third input terminal end the output terminal; there is the fourth switching circuit sub-branch between the fourth input terminal and the output terminals: the output terminal is used as an alternating current terminal.
 6. The five-level topology unit of claim 3, wherein the first switching circuit branch comprises a first bidirectional switch and the second switching circuit branch comprises a second bidirectional switch; the first terminal of the first bidirectional switch is connected with the first terminal of the first switching circuit branch; the second terminal of the first bidirectional switch is connected with the second terminal of the first switching circuit branch; the first terminal of the second bidirectional switch is connected with the first terminal of the second switching circuit branch; the second terminal of the second bidirectional switch is connected with the second terminal of the second switching circuit branch.
 7. The five-level topology unit of claim 4, wherein the circuit module comprises a first bidirectional switch T₃₁, a second bidirectional switch T₃₂, a first diode D₃₁ and a second diode D₃₂; the positive terminal of the first diode D₃₁ is connected with the negative terminal of the second diode D₃₂; the negative terminal of the first diode D₃₁ is connected with the first terminal of the first bidirectional switch T₃₁; the second terminal of the first bidirectional switch T₃₁ is connected with the second terminal of the circuit module; the positive terminal of the second diode D₃₂ is connected with the second terminal of the second bidirectional switch T₃₂; the first terminal of the second bidirectional switch T₃₂ is connected with the third terminal of the circuit module; the common terminal of the first diode D₃₁ and the second diode D₃₂ is connected with the first terminal of the circuit module.
 8. The five-level topology unit of claim 4, wherein the circuit module comprises a bidirectional switch T₅₁, a first diode D₅₁, a second diode D₅₂, a third diode D₅₃, and a fourth diode D₅₄; the positive terminal of the first diode D₅₁ is connected with the first terminal of the circuit module; the negative terminal of the first diode D₅₂ is connected with the first terminal of the bidirectional switch T₅₁; the negative terminal of the third diode D₅₃ is connected with the negative terminal of the first diode D₅₁; the positive terminal of the third diode D₅₃ is connected with the third terminal of the circuit module; the negative terminal of the second diode D₅₂ is connected with the positive terminal of the first diode D₅₁; the positive terminal of the second diode D₅₂ is connected with the second terminal of the bidirectional switch T₅₁; the negative terminal of the fourth diode D₅₄ is connected with the second terminal of the circuit module; the positive terminal of the fourth diode D₅₄ is connected with the positive terminal of the second diode D₅₂.
 9. The five-level topology unit of claim 4, wherein the circuit module comprises a first bidirectional switch T₇₁, a second bidirectional switch T₇₂, a third bidirectional switch T₇₃ and a fourth bidirectional switch T₇₄; the second terminal of the first bidirectional switch T₇₁ is connected with the first terminal of the second bidirectional switch T₇₂; the first terminal of the first bidirectional switch T₇₂ is connected with the first terminal of the third bidirectional switch T₇₃; the second terminal of the third bidirectional switch T₇₃ is connected with the second terminal of the circuit module; the common terminal of the first bidirectional switch T₇₁ and the second bidirectional switch T₇₂ is connected with the first terminal of the circuit module; the second terminal of the second bidirectional switch T₇₂ connected with the second terminal of the fourth bidirectional switch T₇₄; the first terminal of the fourth bidirectional switch T₇₄ is connected with the third terminal of the circuit module.
 10. The five-level topology unit of claim 4, wherein the circuit module comprises a first bidirectional switch T₉₁, a second bidirectional switch T₉₂, a first diode D₉₁˜an eighth diode D₉₈; the positive terminal of the first diode D₉₁ is connected with the negative terminal of the second diode D₉₂; the negative terminal of the first diode D₉₁ is connected with the first terminal of the first bidirectional switch T₉₁; the positive terminal of the second diode D₉₂ is connected with the second terminal of the first bidirectional switch T₉₁; the common terminal of the first diode D₉₁ and the second diode D₉₂ is connected with the first terminal of the circuit module; the positive terminal of the third diode D₉₃ is connected with the negative terminal of the fourth diode D₉₄; the negative of the third diode D₉₃ is connected with the first terminal of the first bidirectional switch T₉₁; the positive terminal of the fourth diode D₉₄ is connected with the second terminal of the first bidirectional switch T₉₁; the common terminal of the third diode D₉₃ and the fourth diode D₉₄ is connected with the second terminal of the circuit module; the positive terminal of the fifth diode D₉₅ is connected with the negative terminal of the sixth diode D₉₆; the negative terminal of the fifth diode D₉₅ is connected with the first terminal of the second bidirectional switch T₉₂; the positive terminal of the sixth diode D₉₆ is connected with the second terminal of the second bidirectional switch T₉₂; the common terminal of the fifth diode D₉₅ and the sixth diode D₉₆ is connected with the first terminal of the circuit module; the positive terminal of the seventh diode D₉₇ is connected with the negative terminal of the eighth diode D₉₈; the negative of the seventh diode D₉₇ is connected with the first terminal of the second bidirectional switch T₉₂; the positive terminal of the eighth diode D₉₈ is connected with the second terminal of the second bidirectional switch T₉₂; the common terminal of the seventh diode Ds and the eighth diode D₉₈ is connected with the third terminal of the circuit module.
 11. The five-level topology unit of claim 7, wherein the circuit module further comprises a third bidirectional switch T₁₁₃ and a fourth bidirectional switch T₁₁₄; the first terminal of the third bidirectional switch T₁₁₃ is connected with the negative terminal of the first diode D₃₁; the second terminal of the third bidirectional switch T₁₁₃ is connected with the first terminal of the fourth bidirectional switch T₁₁₄; the second terminal of the third bidirectional switch T₁₁₄ is connected with the positive terminal of the second diode D₃₂; the common terminal of the third bidirectional switch T₁₁₃ and the fourth bidirectional switch T₁₁₄ is connected with the first terminal of the circuit module.
 12. The five-level topology unit of claim 3, wherein the circuit module further comprises a fifth bidirectional switch T₁₂₅ and a sixth bidirectional switch T₁₂₆; the first terminal of the fifth bidirectional switch T₁₂₅ is connected with the first terminal of the first bidirectional switch T₇₁; the second terminal of the fifth bidirectional switch T₁₂₅ is connected with the first terminal of the circuit module; the first terminal of the sixth bidirectional switch T₁₂₆ is connected with the first terminal of the circuit module; the second terminal of the sixth bidirectional switch T₁₂₆ is connected with the second terminal of the second bidirectional switch T₇₂.
 13. The five-level topology unit of claim 10, wherein the circuit module farther comprises a third bidirectional switch T₁₃₃ and a fourth bidirectional switch T₁₃₄; the first terminal of the third bidirectional switch T₁₃₃ is connected with the first terminal of the first bidirectional switch T₉₁; the second terminal of the third bidirectional switch T₁₃₃ is connected with the first terminal of the circuit module; the first terminal of the fourth bidirectional switch T₁₃₄ is connected with the first terminal of the circuit module; the second terminal of the fourth bidirectional switch T₁₃₄ is connected with the second terminal of the second bidirectional switch T₉₂.
 14. The five-level topology unit of claim 8, wherein the circuit module further comprises a second bidirectional switch T₁₄₂ and a third bidirectional switch T₁₄₃; the first terminal of the second bidirectional switch T₁₄₂ is connected with the first terminal of the first bidirectional switch T₅₁; the second terminal of the second bidirectional switch T₁₄₂ is connected with the first terminal of the circuit module; the first terminal of the third bidirectional switch T₁₄₃ is connected with the first terminal of the circuit module; the second terminal of the third bidirectional switch T₁₄₃ is connected with the second terminal of the first bidirectional switch T₅₁.
 15. The five-level topology unit of any claim from claim 7 to claim 14, wherein the circuit module further comprises a first inductor that connects the first terminal of the circuit module to the common terminal of the first subordinate switching circuit branch and the second subordinate switching circuit branch.
 16. The five-level topology unit of claim 15, wherein the half bridge inverter module is connected with AC utility through a second inductor; the first inductor shares a magnetic core with the second inductor.
 17. The five-level topology unit of claim 5, wherein the first subordinate module comprises a first bidirectional switch T₁₅₁, a second bidirectional switch T₁₅₂ and a first diode D₁; the positive terminal of the first diode D₁ is connected with the first input terminal of the first subordinate module; the negative terminal of the first diode D₁ is connected with the first terminal of the first bidirectional switch T₁₅₁; the second terminal of the first bidirectional switch T₁₅₁ is connected with the first terminal of the second bidirectional switch T₁₅₂; the common terminal of the first bidirectional switch T₁₅₁ and the second bidirectional switch T₁₅₂ is connected with the second input terminal of the first subordinate module; the second terminal of the second bidirectional switch T₁₅₂ is connected with the output terminal of the first subordinate module.
 18. The five-level topology unit of claim 5, wherein the first subordinate module comprises a first bidirectional switch T₁₆₁, a second bidirectional switch T₁₆₂ and a first diode D₁; the positive terminal of the first diode D₁ is connected with the first input terminal of the first subordinate module; the negative terminal of the first diode D₁ connected with the first terminal of the first bidirectional switch T₁₆₁; the second terminal of the first bidirectional switch T₁₆₁ is connected with the output terminal of the first subordinate module; the first terminal of the second bidirectional switch T₁₆₂ is connected with the second input terminal of the first subordinate module; the second terminal of the second bidirectional switch T₁₆₂ is connected with the output terminal of the first subordinate module.
 19. The five-level topology unit of claim 5, wherein the first subordinate module comprises a first bidirectional switch T₁₇₁, a second bidirectional switch T₁₇₂ and a first diode D₁; the positive terminal of the first diode D₁ is connected with the first input terminal of the first subordinate module; the negative terminal of the first diode D₁ is connected with the first terminal of the second bidirectional switch T₁₇₂; the second terminal of the second bidirectional switch T₁₇₂ connected with the output terminal of the first subordinate module; the first terminal of the second bidirectional switch T₁₇₂ is connected with the second of the first bidirectional switch T₁₇₁; the first terminal of the first bidirectional switch T₁₇₁ is connected with the second input terminal of the first subordinate module.
 20. The five-level topology unit of claim 5, wherein the second subordinate module comprises a third bidirectional switch T₁₈₃, a fourth bidirectional switch T₁₈₄ and a second diode D₂; the first terminal of the third bidirectional switch T₁₈₃ is connected with the output terminal of the second subordinate module: the second terminal of the third bidirectional switch T₁₈₃ connected with the third input terminal of the second subordinate module: the first terminal of the fourth bidirectional switch T₁₈₄ is connected with the second terminal of the third bidirectional switch T₁₈₃; the second terminal of the fourth bidirectional switch T₁₈₄ is connected with the positive terminal of the second diode D₂; the negative terminal of the second diode D₂ is connected with the fourth input terminal of the second subordinate module.
 21. The five-level topology unit of claim 5, wherein the second subordinate module comprises a third bidirectional switch T₁₉₃, a fourth bidirectional switch T₁₉₄ and a second diode D₂; the first terminal of the third bidirectional switch T₁₉₃ is connected with the output terminal of the second subordinate module; the second terminal of the third bidirectional switch T₁₉₃ connected with the third input terminal of the second subordinate module; the first terminal of the fourth bidirectional switch T₁₉₄ is connected with the output terminal of the second subordinate module; the second terminal of the fourth bidirectional switch T₁₉₄ is connected with the positive terminal of the second diode D₂; the negative terminal of the second diode D₂ is connected with the fourth input terminal of the second subordinate module.
 22. The five-level topology unit of claim 5, wherein the second subordinate module comprises a third bidirectional switch T₂₀₃, a fourth bidirectional switch T₂₀₄ and a second diode D₂; the first terminal of the third bidirectional switch T₂₀₃ is connected with the output terminal of the second subordinate module; the second terminal of the third bidirectional switch T₂₀₃ is connected with both the first terminal of the fourth bidirectional switch T₂₀₄ and the positive terminal of the second diode D₂; the second terminal of the fourth bidirectional switch T₂₀₄ is connected with the third input terminal of the second subordinate module; the negative terminal of the second diode D₂ is connected with the fourth input terminal of the second subordinate module.
 23. The five-level topology unit of any claim from claim 17 to claim 22, wherein the first diode D₁ is replaced by a ninth bidirectional switch T₉; or the second diode D₂ is replaced by a tenth bidirectional switch T₁₀.
 24. A single phase five-level inverter, comprising: a five-level topology unit of any claim from claim 3 to claim 23; and a controller that provides a control signal for each bidirectional switch in the five-level topology unit so that each bidirectional switch is driven by its own control signal.
 25. The single phase five-level inverter of claim 24, wherein one terminal of AC utility is connected with the common terminal of the first DC power supply and the second DC power supply while the other terminal of AC utility is connected with the half-bridge inverter module.
 26. A three-phase five-level inverter, comprising: three five-level topology units of any claim from claim 3 to claim 23 but both claim 15 and claim 16 with the common first DC power supply and the second DC power supply; and a controller that provides a control signal for each bidirectional switch in the three five-level topology units so that each bidirectional switch is driven by its own control signal; wherein all the first input terminals of the first subordinate modules in the three five-level topology units ere connected with the positive terminal of the first DC power supply; all the first terminals of the circuit modules in the three five-level topology units are connected with the common terminal of the first DC power supply and the second DC power supply; all the fourth input terminals of the second subordinate modules in the three five-level topology units are connected with the negative terminal of the second DC power supply; all the output terminals of the half-bridge inverter modules in the three five-level topology units are connected respectively with the three phase terminals of AC utility.
 27. The three-phase five-level inverter of claim 26, wherein the common terminal of the first DC power supply and the second DC power supply is connected with the neutral terminal of AC utility.
 28. A three-phase five-level inverter, comprising: three five-level topology units of claim 15 or claim 16 with the common first DC power supply and the second DC power supply; and a controller that provides a control signal for each bidirectional switch in the three five-level topology units so that each bidirectional switch is driven by its own control signal; wherein all the circuit modules in the three five-level topology units share the first inductor; all the first input terminals of the first subordinate modules in the three five-level topology units are connected with the positive terminal of the first DC power supply; all the first terminals of the circuit modules in the three five-level topology units are connected with the common terminal of the first DC power supply and the second DC power supply; all the fourth input terminals of the second subordinate modules in the three five-level topology units are connected with the negative terminal of the second DC power supply; all the output terminals of the half-bridge inverter modules in the three five-level topology units are connected respectively with the three phase terminals of AC utility.
 29. The three-phase five-level inverter of claim 28, wherein the common terminal of the first DC power supply and the second DC power supply is connected with the neutral terminal of AC utility. 